12-153 device 80-lead 64-lead 3-sided die in waffle pack 80-lead ceramic gullwing plastic gullwing ceramic gullwing (mil-std-883 processed*) HV7224 HV7224dg HV7224pg HV7224x rbHV7224dg * for hi-rel process flows, refer to page 5-3 of the databook. HV7224 40-channel symmetric row driver ordering information package options general description the hv72 is a low-voltage serial to high-voltage parallel convert- ers with push-pull outputs. it is especially suitable for use as a symmetric row driver in ac thin-film electroluminescent (actfel) displays. when the data reset pin (dr io ) is at logic high, it will reset all the outputs of the internal shift register to zero. at the same time, the output of the shift register will start shifting a logic high from the least significant bit to the most significant bit. the dr io can be triggered at any time. the dir and shift pins control the direction of data shift through the device. when dir is at logic high, dr ioa is the input and dr iob is the output. when dir is grounded, dr iob is the input and the dr ioa is the output. see the output sequence operation table for output sequence. the pol and oe pins perform the polarity select and output enable function respectively. data is loaded on the low to high transition of the clock. a logic high will cause the output to swing to v pp if pol is high, or to gnd if pol is low. all outputs will be in high- z state if oe is at logic high. data output buffers are provided for cascading devices. absolute maximum ratings supply voltage, v dd 1 -0.5v to +7v supply voltage, v pp -0.5v to +260v logic input levels -0.5v to v dd +0.5v continuous total power dissipation 2 plastic 1200mw ceramic 1900mw operating temperature range plastic -40 c to +85 c ceramic -55 c to +125 c storage temperature range -65 c to +150 c lead temperature 1.6mm (1/16 inch) 260 c from case for 10 seconds notes: 1. all voltages are referenced to gnd. 2. for operation above 25 c ambient derate linearly to maximum operating tem- perature at 20mw/ c for plastic and at 19mw/ c for ceramic. features n n processed with hvcmos ? technology n n symmetric row drive (reduces latent imaging in actfel displays) n n output voltage up to 240v n n low-power level shifting n n source/sink current 70ma (min.) n n shift register speed 3mhz n n pin-programmable shift direction (dir, shift) n n hi-rel processing available
12-154 symbol parameter min max units conditions i dd v dd supply current 10 ma f clk = 3mhz i pp high voltage supply current 2.0 ma outputs low or high-z 4.0 ma one output high 1 i ddq quiescent v dd supply current 100 m a all v in = gnd or v dd v oh high-level output hv out 190 v i o = -70ma data out 4.5 v i o = -100 m a v ol low-level output hv out 50 v i o = 70ma data out 0.5 v i o = 100 m a i ih high-level logic input current 1.0 m av ih = v dd i il low-level logic input current -1.0 m av il = 0v i sat saturation current hv out p-ch -80 ma n-ch 75 ma note: 1. only one output can be turned on at a time. electrical characteristics (over recommended operating conditions of v dd = 5v, v pp = 240v, and t a = 25 c unless noted) dc characteristics symbol parameter min max units conditions f clk clock frequency 3.0 mhz t w (h/l) pulse width - clock high or low 150 ns t sud data set-up time before clock rises 50 ns t hd data hold time after clock rises 50 ns t suc hv out delay from clock rises (hi-z to h or l) 1.0 m sc l = 330pf // r l = 10k w t sue hv out delay from output enable falls 600 ns c l = 330pf // r l = 10k w t hc hv out delay from clock rises (h or l to hi-z) 2.0 m sc l = 330pf // r l = 10k w t he hv out delay from output enable rises 600 ns c l = 330pf // r l = 10k w t dhl * delay time clock to data output falls 250 ns c l = 15pf t dlh * delay time clock to data output rises 250 ns c l = 15pf t onf hv out fall time 2.0 m sc l = 330pf // r l = 10k w t onr hv out rise time 2.0 m sc l = 330pf // r l = 10k w t pow pol pulse width 3.0 m s t oew output enable pulse width 3.0 m s slew rate, v pp or gnd 45 v/ m s one active output driving 4.7nf load ac characteristics * the delay is measured from the trailing edge of the clock but the data is triggered by the rising edge of the clock. there i s an internal delay for the data output which is equal to t wh . therefore the delay is measured from the trailing edge of the clock. HV7224
12-155 HV7224 v dd input gnd (logic) v pp gnd (power) hv out logic inputs gnd (logic) data out logic data output high voltage outputs v dd symbol parameter min max units v dd logic supply voltage 4.5 5.5 v v pp high voltage supply ? 0 240 v v ih high-level input voltage 0.7 v dd v dd v v il low-level input voltage 0 0.2v dd v f clk clock frequency 3 mhz i o high voltage output current 70 ma t a operating free-air temperature plastic -40 +85 c ceramic -55 +125 c i od allowable pulse current through output diode 300 ma notes: ? output will not switch at v pp = 0v. power-up sequence should be the following: 1. connect ground. 2. apply v dd . 3. set all inputs (data, clk, enable, etc.) to a known state. 4. apply v pp . power-down sequence should be the reverse of the above. recommended operating conditions input and output equivalent circuits
12-156 HV7224 switching waveforms data reset input (dr ioa /dr iob ) 50% 50% t pow data reset output (dr ioa /dr iob ) t hd 50% 50% v ih v il high impedance 90% 10% 10% hv out hv out 90% t sue t onr 90% t he 10% 50% t dlh 50% t dhl 50% t oew 50% high impedance high impedance high impedance 90% 10% 10% 90% t suc t onr 90% t hc 10% hv out (pol = h) hv out (pol = l) pol oe data valid t sud data valid clk t wl l/f clk 50% 50% 50% 50% t wh t suc t onf t hc t sue t onf t he v ih v il v oh v oh v ol v ih v il v ol v ih v il v oh v ol
12-157 HV7224 dir shift data reset in data reset out hv out # sequence direction* option (see pin-out on p. 12-158) ll dr iob dr ioa 1 40 ? 1a hl dr ioa dr iob 2 1 ? 40 a lh dr iob dr ioa 1 20 ? 1 ? 40 ? 21 b hh dr ioa dr iob 2 21 ? 40 ? 1 ? 20 b functional block diagram i/o relations inputs clk dir s/r data pol oe hv outputs o/p high x x h h l h o/p off x x l x l high-z o/p low x x h l l l o/p off x x x x h all o/p high-z function table * reference to package outline or chip layout drawing. 1.dr ioa is dr iob delayed by 40 clock pulses. 2. dr iob is dr ioa delayed by 40 clock pulses. output sequence operation table notes : h = logic high level, l = logic low level, x = irrelevant data input (dr io ) loaded on the low-to-high transistion of the clock. hv out 1 hv out 2 hv out 40 oe clk s/r dir polarity shift p lt n lt lt gnd lt = level translator v dd v pp d ioa d iob
12-158 HV7224 hv72 option a: pin function pin function 1hv out 1/40 33 n/c 2hv out 2/39 34 dr iob 3hv out 3/38 35 oe 4hv out 4/37 36 nc 5hv out 5/36 37 pol 6hv out 6/35 38 n/c 7hv out 7/34 39 v dd 8hv out 8/33 40 n/c 9hv out 9/32 41 gnd (logic) 10 hv out 10/31 42 gnd (power) 11 hv out 11/30 43 n/c 12 hv out 12/29 44 v pp 13 hv out 13/28 45 hv out 21/20 14 hv out 14/27 46 hv out 22/19 15 hv out 15/26 47 hv out 23/18 16 hv out 16/25 48 hv out 24/17 17 hv out 17/24 49 hv out 25/16 18 hv out 18/23 50 hv out 26/15 19 hv out 19/22 51 hv out 27/14 20 hv out 20/21 52 hv out 28/13 21 v pp 53 hv out 29/12 22 n/c 54 hv out 30/11 23 gnd (power) 55 hv out 31/10 24 gnd (logic) 56 hv out 32/9 25 dir 57 hv out 33/8 26 v dd 58 hv out 34/7 27 clk 59 hv out 35/6 28 n/c 60 hv out 36/5 29 shift 61 hv out 37/4 30 n/c 62 hv out 38/3 31 dr ioa 63 hv out 39/2 32 n/c 64 hv out 40/1 note: pin designation for dir h/l, shift = l. example: for dir = h, pin 1 is hv out 1. for dir = l, pin 1 is hv out 40. pins 65C80 are nc (ceramic only). pin configurations hv72 option b: pin function pin function 1hv out 20/21 33 n/c 2hv out 19/22 34 dr iob 3hv out 18/23 35 oe 4hv out 17/24 36 n/c 5hv out 16/25 37 pol 6hv out 15/26 38 n/c 7hv out 14/27 39 v dd 8hv out 13/28 40 n/c 9hv out 12/29 41 gnd (logic) 10 hv out 11/30 42 gnd (power) 11 hv out 10/31 43 n/c 12 hv out 9/32 44 v pp 13 hv out 8/33 45 hv out 40/1 14 hv out 7/34 46 hv out 39/2 15 hv out 6/35 47 hv out 38/3 16 hv out 5/36 48 hv out 37/4 17 hv out 4/37 49 hv out 36/5 18 hv out 3/38 50 hv out 35/6 19 hv out 2/39 51 hv out 34/7 20 hv out 1/40 52 hv out 33/8 21 v pp 53 hv out 32/9 22 n/c 54 hv out 31/10 23 gnd (power) 55 hv out 30/11 24 gnd (logic) 56 hv out 29/12 25 dir 57 hv out 28/13 26 v dd 58 hv out 27/14 27 clk 59 hv out 26/15 28 n/c 60 hv out 25/16 29 shift 61 hv out 24/17 30 n/c 62 hv out 23/18 31 dr ioa 63 hv out 22/19 32 n/c 64 hv out 21/20 note: pin designation for dir l/h, shift = h. example: for dir = l, pin 1 is hv out 20. for dir = h, pin 1 is hv out 21. pins 65C80 are nc (ceramic only).
12-159 HV7224 index 1 24 64 41 25 40 top view 3-sided plastic 64-pin gullwing package package outline 65 80 1 24 25 40 41 64 index top view 80-pin ceramic gullwing package
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